Heng Email
ASIC设计师 @ Bridgecom Semiconductors
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Heng Work
- 2022 -now ASIC设计师 @
- 2019 -2022 ASIC Design Engineer @
- 2015 -2019 Senior Digital Design Engineer @
- 2013 -2015 Digital Design and Verification Engineer Intern @
Heng Education
- Xidian University
硕士 (Integrated Circuit Design)
2012-2015 - Xidian University
Bachelor's degree (Microelectronics)
2008-2012
Heng Skills
- ASIC
- VHDL
- Verilog
- System Verilog
- Jasper
- Formal Verification
- Spyglass
- SoC
- PMIC
- SVA
- 半导体
- 系统芯片
- 功能验证
- 集成电路
- RTL 设计
- 超大规模集成电路
- 集成电路设计
- Python
- Semiconductors
- UVM
- VCS
- Perl
Heng Summary
- Heng, is currently a ASIC设计师 at United Micro Technology. Heng brings experience from previous roles at 浪潮 and Intel Corporation. Heng holds a 2012 - 2015 硕士 in Integrated Circuit Design @ Xidian University. With a robust skill set that includes ASIC, VHDL, Verilog, System Verilog, Jasper and more. Heng has 1 emails on RocketReach.
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