Hema T Email
Senior ASIC Verification Engineer
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Hema T Location
- United States
Hema T Work
- 2013 -now Senior ASIC Verification Engineer @ Qualcomm
- 2011 -2013 R and D Enginner @ IBM INDIA
- 2010 -2011 Senior Technical Member @
- 2006 -2010 Senior Project Engineer @
Hema T Education
- Anna University
Bachelor of Engineering (B.E.) (Electronics and Communication Engineering)
2002-2006
Hema T Skills
- System Verilog, OVM, UVM
- ASIC Verification
- Cadence ncsim, Synopsys VCS
- Functional Coverage, Assertions
- ASIC
- Verilog
- VLSI
- SystemVerilog
- Functional Verification
- VHDL
- UVM
- Open Verification Methodology
- Debugging
- Simulations
- C
- FPGA
- Embedded Systems
- Open Verification
- Synopsys
- Cadence Ncsim
- System Verilog
- Functional Coverage
- OVM
- Synopsys Vcs
- Verification
- Assertions
Hema T Summary
- Hema T, based in United States, is currently a Senior ASIC Verification Engineer at Qualcomm. Hema T brings experience from previous roles at IBM INDIA, KPIT Cummins Infosystems Limited and Wipro Technologies. Hema T holds a 2002 - 2006 Bachelor of Engineering (B.E.) in Electronics and Communication Engineering @ Anna University. With a robust skill set that includes System Verilog, OVM, UVM, ASIC Verification, Cadence ncsim, Synopsys VCS, Functional Coverage, Assertions, ASIC and more. Hema T has 1 emails on RocketReach.
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