Design Engineer @ Texas Instruments (July 2004 - February 2007)
Harsh Setia Education
Thapar Institute of Engineering & Technology
Bachelor of Engineering (B.E.) (Electronics(I&C))
2000-2004
DAV College, Chandigarh 1998-2000
Harsh Setia Skills
ASIC
C/C++
Cache
Digital Signal Processors
Formal Verification
Functional Verification
H.264
IC
Integrated Circuit Design
Memory
Memory Subsystems
ModelSim
NCSim
Open Verification Methodology
Processors
RTL Design
SoC
Specman
SystemVerilog
Timing Closure
VHDL
VLSI
Verilog
Video
Testing
Integrated Circuit
Digital Signal
SQL
Verification
Business Analysis
InDesign
Strategic Planning
Customer Service
Microsoft Excel
Open Verification
Harsh Setia Summary
Harsh Setia, based in Bengaluru, KA, IN, is currently a Senior Director - Verification at Intel. Harsh Setia brings experience from previous roles at Samsung Semiconductor India R&D Center. Harsh Setia holds a 2000 - 2004 Bachelor of Engineering (B.E.) in Electronics(I&C) @ Thapar Institute of Engineering & Technology. With a robust skill set that includes ASIC, C/C++, Cache, Digital Signal Processors, Formal Verification and more. Harsh Setia has 5 emails and 1 mobile phone numbers on RocketReach.
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