Harsh Setia Email & Phone Number
Senior Director - Verification @ Intel Corporation
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Harsh Setia Location
- Bengaluru, KA, IN
Harsh Setia Work
- 2026 -now Senior Director - Verification @
- 2021 -2026 Director @ Samsung Semiconductor India R&D Center
- 2018 -2021 Associate Director @ Samsung Semiconductor India R&D Center
- 2016 -2018 Senior Chief Engineer @ Samsung Semiconductor India R&D Center
- 2014 -2016 Chief Engineer @ Samsung Semiconductor India R&D Center
- 2014 -2014 Senior Lead Engineer - Verification @
- 2010 -2013 Verification Expert @
- 2007 -2010 Senior Design Engineer @
- 2004 -2007 Design Engineer @
Harsh Setia Education
- Thapar Institute of Engineering & Technology
Bachelor of Engineering (B.E.) (Electronics(I&C))
2000-2004 - DAV College, Chandigarh 1998-2000
Harsh Setia Skills
- VLSI
- Functional Verification
- Specman
- ModelSim
- SystemVerilog
- SoC
- RTL design
- ASIC
- Verilog
- VHDL
- NCSim
- Formal Verification
- C/C++
- H.264
- Cache
- Memory Subsystems
- Video
- Memory
- Digital Signal Processors
- IC
- Processors
- Integrated Circuit Design
- Open Verification Methodology
- Timing Closure
- Testing
- Integrated Circuit
- Digital Signal
- SQL
- Verification
- Business Analysis
- InDesign
- Strategic Planning
- Customer Service
- Microsoft Excel
- Open Verification
Harsh Setia Summary
- Harsh Setia, based in Bengaluru, KA, IN, is currently a Senior Director - Verification at Intel. Harsh Setia brings experience from previous roles at Samsung Semiconductor India R&D Center. Harsh Setia holds a 2000 - 2004 Bachelor of Engineering (B.E.) in Electronics(I&C) @ Thapar Institute of Engineering & Technology. With a robust skill set that includes VLSI, Functional Verification, Specman, ModelSim, SystemVerilog and more. Harsh Setia has 4 emails and 1 mobile phone numbers on RocketReach.
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