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Harsh Setia Location
Bengaluru, KA, IN
Harsh Setia Work
Senior Director - Verification @ (January 2026 - Present)
Director @ Samsung Semiconductor India R&D Center (March 2021 - January 2026)
Associate Director @ Samsung Semiconductor India R&D Center (March 2018 - February 2021)
Senior Chief Engineer @ Samsung Semiconductor India R&D Center (March 2016 - February 2018)
Chief Engineer @ Samsung Semiconductor India R&D Center (May 2014 - February 2016)
Senior Lead Engineer - Verification @ (January 2014 - May 2014)
Verification Expert @ (February 2010 - December 2013)
Senior Design Engineer @ (February 2007 - February 2010)
Design Engineer @ (July 2004 - February 2007)
Harsh Setia Education
Thapar Institute of Engineering & Technology
Bachelor of Engineering (B.E.) (Electronics(I&C))
2000-2004
DAV College, Chandigarh 1998-2000
Harsh Setia Skills
VLSI
Functional Verification
Specman
ModelSim
SystemVerilog
SoC
RTL design
ASIC
Verilog
VHDL
NCSim
Formal Verification
C/C++
H.264
Cache
Memory Subsystems
Video
Memory
Digital Signal Processors
IC
Processors
Integrated Circuit Design
Open Verification Methodology
Timing Closure
Testing
Integrated Circuit
Digital Signal
SQL
Verification
Business Analysis
InDesign
Strategic Planning
Customer Service
Microsoft Excel
Open Verification
Harsh Setia Summary
Harsh Setia, based in Bengaluru, KA, IN, is currently a Senior Director - Verification at Intel. Harsh Setia brings experience from previous roles at Samsung Semiconductor India R&D Center. Harsh Setia holds a 2000 - 2004 Bachelor of Engineering (B.E.) in Electronics(I&C) @ Thapar Institute of Engineering & Technology. With a robust skill set that includes VLSI, Functional Verification, Specman, ModelSim, SystemVerilog and more. Harsh Setia has 5 emails and 1 mobile phone numbers on RocketReach.
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