Harsh Patil Email & Phone Number
Distinguished Engineer @ Apple
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Harsh Patil Location
- Cupertino, CA, US
Harsh Patil Work
- Distinguished Engineer @ (March 2025 - Present)
- Principal Engineer - System Architecture and Design @ (January 2022 - March 2025)
- Lead Architect - System Architecture and Design @ (April 2016 - January 2022)
- Server Systems Performance Architect @ (July 2015 - April 2016)
- Snapdragon Performance and Low Power SoC Architect @ (July 2013 - July 2015)
- Senior Hardware Engineer @ (January 2013 - July 2013)
- Hardware Engineer lll @ (January 2008 - July 2013)
- Hardware Engineer lll @ (January 2008 - July 2013)
- Hardware Intern @ Cisco Systems Inc (April 2007 - September 2007)
Harsh Patil Education
- University of Michigan
Master's (Electrical Engineering: Systems)
2006-2007 - Visvesvaraya Technological University
Bachelor's in Engineering (Electronics & Communication)
2001-2005
Harsh Patil Skills
- ASIC
- Algorithms
- Application-Specific Integrated Circuits (ASIC)
- C
- C++
- ClearCase
- Computer Architecture
- Debugging
- Digital Design
- Digital Electronics
- Embedded Systems
- Functional Verification
- Git
- Hardware
- Hardware Architecture
- IC
- IPv6
- Logic Design
- Matlab
- Microprocessors
- Network Processors
- OpenGL Shading Language (GLSL)
- Perl
- Processors
- Programming
- Python
- QoS
- RTL Design
- Scripting
- Simulations
- SoC
- System Architecture
- System on a Chip (SoC)
- SystemC
- SystemVerilog
- TCL
- TCP/IP
- Tensorflow
- Test Planning
- Testing
- UVM
- Unix
- VHDL
- VLSI
- VMM
- Verilog
- Very-Large-Scale Integration (VLSI)
- keras
- openCL
- openGL
- System on a Chip Soc
- ARM
- Application Specific Integrated Circuits Asic
- FPGA
- Opengl Shading Language Glsl
- Very Large Scale Integration Vlsi
- Device Drivers
- Application Specific Integrated Circuits
- Very Large Scale Integration
- System on a Chip
- Opengl Shading Language
Harsh Patil Summary
- Harsh Patil, based in Cupertino, CA, US, is currently a Distinguished Engineer at Apple. Harsh Patil brings experience from previous roles at Apple and Qualcomm. Harsh Patil holds a 2006 - 2007 Master's in Electrical Engineering: Systems @ University of Michigan. With a robust skill set that includes ASIC, Algorithms, Application-Specific Integrated Circuits (ASIC), C, C++ and more. Harsh Patil has 2 emails and 2 mobile phone numbers on RocketReach.
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