Harsh Patil's Location
Cupertino, CA, US
Harsh Patil's Work
- Principal Engineer - System Architecture and Design @ Apple
- Lead Architect - System Architecture and Design @ Apple
- Server Systems Performance Architect @ Qualcomm
- Snapdragon Performance and Low Power SoC Architect @ Qualcomm
- Senior Hardware Engineer @ Cisco
- Hardware Engineer lll @ Cisco
- Hardware Engineer lll @ Cisco
- Hardware Intern @ The Learning Net Ltd.
Harsh Patil's Education
- University of Michigan
Master's (Electrical Engineering: Systems)
2006 - 2007 - Visvesvaraya Technological University
Bachelor's in Engineering (Electronics & Communication)
2001 - 2005
Harsh Patil's Skills
- Hardware Architecture
- Logic Design
- Git
- Computer Architecture
- Digital Electronics
- Test Planning
- Algorithms
- C
- Debugging
- System on a Chip Soc
Harsh Patil's Summary
Harsh Patil, based in Cupertino, CA, US, is currently a Principal Engineer - System Architecture and Design at Apple, bringing experience from previous roles at Apple, Qualcomm and Cisco Systems. Harsh Patil holds a 2006 - 2007 Master's in Electrical Engineering: Systems @ University of Michigan. With a robust skill set that includes Hardware Architecture, Logic Design, Git, Computer Architecture, Digital Electronics and more, Harsh Patil contributes valuable insights to the industry. Harsh Patil has 4 emails and 1 mobile phone number on RocketReach.
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