Harsh Patel's Location
Austin, Texas, United States
Harsh Patel's Work
- Circuit Design Engineer @ Rivo
- Senior Silicon Design Engineer @ AMD
- Principal Engineer @ GlobalFoundries
- Research Assistant @ University of Virginia
- Summer Intern @ NVIDIA
- Sr. Design Engineer @ STMicroelectronics
- Lecturer @ V.V.P. Engineering College
- Verification Interns at Z Server verification Team, Banglore @ IBM
Harsh Patel's Education
- University of Virginia
Doctor of Philosophy (Ph.D.) (Electrical and Electronics Engineering)
2013 - 2017 - Vellore Institute of Technology
M.Tech. (VLSI Design)
2007 - 2009 - Dharmsing Desai University
B.E. (Electronics And Communication)
2002 - 2006
Harsh Patel's Skills
- Verilog
- VLSI
- ASIC
- EDA
- Static Timing Analysis
- Integrated Circuit Design
- SystemVerilog
- ModelSim
- RTL design
- Algorithms
Harsh Patel's Summary
Harsh Patel, based in Austin, Texas, United States, is currently a Circuit Design Engineer at Rivos Inc, bringing experience from previous roles at AMD, GLOBALFOUNDRIES, University of Virginia and NVIDIA. Harsh Patel holds a 2013 - 2017 Doctor of Philosophy (Ph.D.) in Electrical and Electronics Engineering @ University of Virginia. With a robust skill set that includes Verilog, VLSI, ASIC, EDA, Static Timing Analysis and more, Harsh Patel contributes valuable insights to the industry. Harsh Patel has 2 emails on RocketReach.
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