Hang Li's Location

San Francisco, California, United States

Hang Li's Work

Hang Li's Education

  • University of Southern California

    Master of Science ( Electrical Engineering - VLSI)

    2011 - 2013
  • Tianjin University of Science and Technology

    Bachelor of Engineering ( Electrical Engineering)

    2007 - 2011

Hang Li's Skills

  • RTL design
  • Digital IC Design
  • Integrated Circuit Design
  • VLSI circuit design based on Cadence Tools
  • Board Level
  • Physical Design
  • Cadence Virtuoso
  • Computer Architecture
  • FPGA
  • RTL verification

Hang Li's Summary

Hang Li, based in San Francisco, California, United States, is currently a Senior Firmware Engineer at Foit/Avago, bringing experience from previous roles at 3d Systems Corporation. Hang Li holds a 2011 - 2013 Master of Science in Electrical Engineering - VLSI @ University of Southern California. With a robust skill set that includes RTL design, Digital IC Design, Integrated Circuit Design, VLSI circuit design based on Cadence Tools, Board Level and more, Hang Li contributes valuable insights to the industry. Hang Li has 2 emails and 1 mobile phone number on RocketReach.

Redirecting you to the search page.

If you're not automatically redirected, please click here

Not the Hang Li you were looking for?

Find contact details for 700 million professionals.

Others Named Hang Li

How It Works
Get a Free Account
Sign up for a free account. No credit card required. Up to 5 free lookups / month.
Search
Search over 700 million verified professionals across 35 million companies.
Get Contact Info
Get contact details including emails and phone numbers (business & personal).
High Performer Summer 2022 RocketReach is a leader in Lead Intelligence on G2 RocketReach is a leader in Lead Intelligence on G2 RocketReach is a leader in Lead Intelligence on G2
talentculture2022
g2crowd
G2Crowd Trusted
chromestore
300K+ Plugin Users