Chip Design Engineer @ (December 2022 - December 2024)
ASIC Management Architect @ (May 2020 - February 2023)
Chip Design Verification Engineer @ (May 2020 - September 2020)
Chip Design Verification Engineer @ (August 2019 - May 2020)
Chip Design Verification Student @ (March 2017 - July 2019)
Guy Harel Education
Technion - Israel Institute of Technology
B.Sc Electrical Engineering
2015-2019
The Hebrew Reali School 1998-2010
Guy Harel Summary
Guy Harel, based in Israel, is currently a Senior ASIC Management Architect at NVIDIA. Guy Harel brings experience from previous roles at NVIDIA and Mellanox Technologies. Guy Harel holds a 2015 - 2019 B.Sc Electrical Engineering @ Technion - Israel Institute of Technology. Guy Harel has 1 emails on RocketReach.
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