Gur Eliash Email & Phone Number
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Gur Eliash Location
- Israel
Gur Eliash Work
- CEO @ (June 2006 - Present)
- Project Manager @ (April 2018 - January 2021)
- Chip Verification Team Leader @ (January 2005 - January 2006)
- VLSI designer @ Rafael (January 1999 - January 2003)
Gur Eliash Education
- Technion - Israel Institute of Technology 1997-2000
Gur Eliash Skills
- ASIC
- VLSI
- Verilog
- Functional Verification
- AMBA AHB
- AXI
- VMM
- Specman
- FPGA
- Ethernet
- USB
- SystemVerilog
- SoC
- FPGA prototyping
- UVM
- Board Support Package
- Xilinx
- Altera
- IEEE1588
- FPGA Verification
- Open Verification Methodology
- Conformal LEC
- IC
- Firmware
- ARM
- Debugging
- EDA
- Embedded Systems
- Hardware Architecture
- Simulations
- Microsoft Excel
- Illustrator
- CVS
- Project Management
- Testing
- Verification
- Technology
Gur Eliash Summary
- Gur Eliash, based in Israel, is currently a CEO at CVS - VLSI Chip Design Verification & Design. Gur Eliash brings experience from previous roles at Innoviz Technologies, Tehuti-networks and Rafael. Gur Eliash holds a 1997 - 2000 Technion - Israel Institute of Technology. With a robust skill set that includes ASIC, VLSI, Verilog, Functional Verification, AMBA AHB and more. Gur Eliash has 1 emails on RocketReach.
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