Guanlin Zhang Email & Phone Number
Lead Analog and Mixed-signal design in 28Gbs SerDes for Intel A10 and S10 FPGA, PLL and CDR and CTLE and VGA @ Intel Corporation
Guanlin Zhang's Location
Santa Clara, CA, US
Guanlin Zhang's Work
- Lead Analog and Mixed-signal design in 28Gbs SerDes for Intel A10 and S10 FPGA, PLL and CDR and CTLE and VGA @ Intel Corporation
- Senior Staff Hardware Developer @ Oracle
Guanlin Zhang's Education
- University of California, Irvine
(Electrical & Computer Engineering)
- Nanjing University
(Physics & Electrical Engineering)
Guanlin Zhang's Skills
- PLL
- SERDES
- Analog Circuit Design
- Mixed-Signal IC Design
- Frequency Synthesizers
- CDR
- Verilog-A
- Verilog-AMS
- Analog Signal Processing
- Analog Behavior Modeling
Guanlin Zhang's Summary
Guanlin Zhang, based in Santa Clara, CA, US, is currently a Lead Analog and Mixed-signal design in 28Gbs SerDes for Intel A10 and S10 FPGA, PLL and CDR and CTLE and VGA at Intel Corporation, bringing experience from previous roles at Oracle. Guanlin Zhang holds a University of California, Irvine. With a robust skill set that includes PLL, SERDES, Analog Circuit Design, Mixed-Signal IC Design, Frequency Synthesizers and more, Guanlin Zhang contributes valuable insights to the industry. Guanlin Zhang has 5 emails and 1 mobile phone number on RocketReach.
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