Grace Sebastian Email
EDA tools Hardware Engineer @ Intel Corporation
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Grace Sebastian Location
- Bengaluru, KA, IN
Grace Sebastian Work
- 2020 -now EDA tools Hardware Engineer @
- 2018 -2020 Senior Engineer @
- 2013 -2018 Design engineer @
Grace Sebastian Education
- Govt. engg college Bartonhill
Bachelor of Technology (B.Tech.) (Electronics and Communications Engineering)
2009-2013 - GHSS Cottonhill
Plus two (Computer Science)
2007-2009
Grace Sebastian Skills
- VLSI
- Cadence Virtuoso
- Cadence Virtuoso Layout Editor
- cadence skill
- Cadence Spectre
- cadence pvs
- Layout Versus Schematic (LVS)
- analog layout
- memory layout
- Standard cell layout
- LVS
- DRC
- Python
- Shell Scripting
- Perl
- TCL
- C++
- HTML
- IC validator
- HSIO
- Matlab
- Layout Versus Schematic Lvs
- Layout Versus Schematic
Grace Sebastian Summary
- Grace Sebastian, based in Bengaluru, KA, IN, is currently a EDA tools Hardware Engineer at Intel Corporation. Grace Sebastian brings experience from previous roles at Altran and Zia Semiconductor Pvt Ltd. Grace Sebastian holds a 2009 - 2013 Bachelor of Technology (B.Tech.) in Electronics and Communications Engineering @ Govt. engg college Bartonhill. With a robust skill set that includes VLSI, Cadence Virtuoso, Cadence Virtuoso Layout Editor, cadence skill, Cadence Spectre and more. Grace Sebastian has 2 emails on RocketReach.
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