Girish R Email

SOC Validation Manager - UWB, NFC Readers and Access Solutions @ NXP Semiconductors

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Girish R's Location

India

Girish R's Work

SOC Validation Manager - UWB, NFC Readers and Access Solutions @ NXP Semiconductors
Lead Post Silicon Validation Engineer @ NXP Semiconductors
Staff Application Engineer @ Broadcom

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Sr Engineer @ Seagate Technology
Post Silicon Electrical Validation Engineer @ Intel Corporation

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Girish R's Education

PES Institute of Technology
M Tech (VLSI Design and Embedded Systems)
2006 - 2008
SJBIT
Bachelor of Engineering (BE) (Electrical, Electronics and Communications Engineering)
2001 - 2005

Girish R's Skills

Python
Analog Validation
Silicon Validation

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Mixed Signal
Analog
ASIC
Processors
Intel
SoC
USB

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Girish R's Summary

Girish R, based in India, is currently a SOC Validation Manager - UWB, NFC Readers and Access Solutions at NXP Semiconductors, bringing experience from previous roles at NXP Semiconductors, Broadcom Inc., Seagate Technology and Intel Corporation. Girish R holds a 2006 - 2008 M Tech in VLSI Design and Embedded Systems @ PES Institute of Technology. With a robust skill set that includes Python, Analog Validation, Silicon Validation, Mixed Signal, Analog and more, Girish R contributes valuable insights to the industry. Girish R has 2 emails on RocketReach.

Girish R Email Address

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