Giacomo Rinaldi's Location
San Diego, CA, US
Giacomo Rinaldi's Work
- VP of Enginnering @ Chronos Tech
- Project Lead and Architect @ Intel Corporation
- Chip Lead and Architect @ Vitesse Semiconductor is now Microsemi
- Staff Analog Design Engineer @ Intel Corporation
- Analog Design Engineer @ STMicroelectronics
- HW and SW Engineer @ Esaote
Giacomo Rinaldi's Education
- Università degli Studi di Firenze
MSEE (Telecommunication Technology)
1993 - 2000 - University of Phoenix
MBA (General Management)
2004 - 2006
Giacomo Rinaldi's Skills
- Ethernet
- Mixed Signal
- Analog
- Analog Circuit Design
- ASIC
- IC
- Semiconductors
- CMOS
- SERDES
- Verilog
Giacomo Rinaldi's Summary
Giacomo Rinaldi, based in San Diego, CA, US, is currently a VP of Enginnering at Chronos Tech, bringing experience from previous roles at Intel, Vitesse Semiconductor and STMicroelectronics. Giacomo Rinaldi holds a 1993 - 2000 MSEE in Telecommunication Technology @ Università degli Studi di Firenze. With a robust skill set that includes Ethernet, Mixed Signal, Analog, Analog Circuit Design, ASIC and more, Giacomo Rinaldi contributes valuable insights to the industry. Giacomo Rinaldi has 3 emails and 1 mobile phone number on RocketReach.
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