Gerald Cunanan Email
IC Mask and layout Engineer @ NXP Semiconductors
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Gerald Cunanan Location
- Arnhem-Nijmegen Metropolitan, GE, NL
Gerald Cunanan Work
- 2012 -now IC Mask and layout Engineer @
- 2007 -2012 IC Mask and layout Engineer @ Sanyo Semiconductor Manufacturing Philippines
Gerald Cunanan Education
- Holy Angel University
Bachelor of Engineering (B.Eng.) (Electronics and Communications Engineering)
2002-2007
Gerald Cunanan Skills
- Cadence Virtuoso
- Floorplanning
- Layout Versus Schematic Lvs
- BiCMOS
- Analog
- Design Rule Checking Drc
- PLL
- Integrated Circuits Ic
- Mixed Signal
- CMOS
- LVS
- SoC
- Training
- EDA
- IC layout
- Travel
- DRC
- Semiconductors
- Physical Design
- Design
- IC
- Design Rule Checking
- Layout Versus Schematic
- Integrated Circuits
Gerald Cunanan Summary
- Gerald Cunanan, based in Arnhem-Nijmegen Metropolitan Area, GE, NL, is currently a IC Mask and layout Engineer at NXP Semiconductors. Gerald Cunanan brings experience from previous roles at Sanyo Semiconductor Manufacturing Philippines. Gerald Cunanan holds a 2002 - 2007 Bachelor of Engineering (B.Eng.) in Electronics and Communications Engineering @ Holy Angel University. With a robust skill set that includes Cadence Virtuoso, Floorplanning, Layout Versus Schematic Lvs, BiCMOS, Analog and more. Gerald Cunanan has 3 emails on RocketReach.
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