Garima Tomar Email
Standard Cells Layout Design Sr Engineer @ Synopsys Inc
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Garima Tomar Location
- Hyderabad, IN
Garima Tomar Work
- 2024 -now Standard Cells Layout Design Sr Engineer @
- 2024 -2024 Standard Cells Layout Design Intern @
- 2023 -2024 Product Validation Intern @
- 2022 -2023 Teaching Assistant @
Garima Tomar Education
- National Institute of Technology, Kurukshetra, Haryana
Master of Technology - MTech (VLSI Design)
2022-2024 - Meerut Institute of Engineering and Technology(MIET)
Garima Tomar Summary
- Garima Tomar, based in Hyderabad, IN, is currently a Standard Cells Layout Design Sr Engineer at Synopsys Inc. Garima Tomar brings experience from previous roles at Synopsys Inc, Cadence Design Systems and National Institute of Technology, Kurukshetra, Haryana. Garima Tomar holds a 2022 - 2024 Master of Technology - MTech in VLSI Design @ National Institute of Technology, Kurukshetra, Haryana. Garima Tomar has 1 emails on RocketReach.
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