Foresemi Microelectronics Information

We are committed to developing hardware-accelerated coprocessor IPs, including hardware security acceleration IPs (HSM, RNG, PUF, AES/ECC/SHA/SMx/etc), trigonometric function hardware acceleration IPs (TMU), compression and decompression hardware acceleration IPs, and edge AI inference IPs based on DCIM, etc. Based on our silicon-proven DesignHaven™ series of security and safety IPs (including international and Chinese cryptographic algorithms, TRNG, PUF, Error Correction Code (ECC) algorithms, etc.), Foresemi’s innovative CryptCompiler® platform can automatically generate and optimize the hardware security IP subsystem and firmware security IP packages. With the CryptCompiler® platform, the security IP delivery time is significantly reduced from weeks to minutes, ensuring higher quality, smaller area, lower power consumption, and faster security application development. This accelerates the integration of security subsystems into SoC chips and the development of security-driven applications, reducing cost and shortening time-to-market (TTM).