Firas Kallel Email & Phone Number
FPGA development Team Leader @ KPIT
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Firas Kallel Location
- Tunis, Tunis, Tunisia
Firas Kallel Work
- 2025 -now FPGA development Team Leader @
- 2019 -2024 FPGA and Embedded Software Developer @
- 2014 -2019 Embedded Software Consultant @
- 2009 -2014 FPGA Design and Verification Engineer @
- 2007 -2009 Analog IC Design Engineer @
- 2007 -2007 Analog IC Design Trainee @
- 2006 -2006 Analog IC Design Trainee @
Firas Kallel Education
- National Engineering School of Sfax TUNISIA
Master (Electronic and Telecommunication)
2008-2009 - National Engineering School of Sfax TUNISIA
Engineer (Microelectronic)
2004-2007 - IEEE International Conference
(Design and Test of Integrated Circuits (DTIS) in Nanoscale Technology. September 2006 TUNISIA)
- Third RAMSIS Summer School
(WiMAX Radio Design – Circuit and System Design Challenges. July 2007 TUNISIA)
Firas Kallel Skills
- Tanner
- RTL verification
- ModelSim
- Hardware Architecture
- Cadence Spectre
- Analog Circuit Design
- VHDL
- VCO
- Quartus
- DVB
- Cadence Virtuoso
- Altera
- Verilog
- Integrated Circuit Design
- Cadence Analog Artist
- RTL design
- FPGA
- C
- TCL
- DRC
- Simulations
- IC
- Software Development
- Single Euro Payments Area Sepa
- Testing
- Management
- Payment Systems
- Engineering
- Microsoft Office
- Embedded Software
- Analog
- EMV
- Design
- Single Euro Payments Area
- C++
- Embedded Systems
- Internet of Things
- Embedded C
- Linux
- Matlab
- Digital Electronics
- Electronics
Firas Kallel Summary
- Firas Kallel, based in Tunis, Tunis, Tunisia, is currently a FPGA development Team Leader at KPIT. Firas Kallel brings experience from previous roles at Primatec Engineering and Telnet. Firas Kallel holds a 2008 - 2009 Master in Electronic and Telecommunication @ National Engineering School of Sfax TUNISIA. With a robust skill set that includes Tanner, RTL verification, ModelSim, Hardware Architecture, Cadence Spectre and more. Firas Kallel has 3 emails and 1 mobile phone numbers on RocketReach.
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