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Fernando Bolanos Location
Boise, ID, US
Fernando Bolanos Work
2021 -now Senior FPGA Designer @
2013 -2022 PCB Design Engineer @
2007 -2022 R and D Electronic Engineer @
2001 -2007 R and D Electronic Design Engineer @
1996 -2001 R and D Electronic Engineer @
Fernando Bolanos Education
ITESO Universidad Jesuita de Guadalajara
M.E. (Electronic Digital Design)
1994-1996
ITESO Universidad Jesuita de Guadalajara
B.Sc. (Electronic)
1986-1990
Fernando Bolanos Skills
Cadence Schematic Capture
Hardware Architecture
Digital Electronics
Linux
Perl
ARM
Microprocessors
PCB design
Electronics
ASIC
Verilog
ClearCase
Xilinx
Programming
Allegro
Embedded Systems
Testing
FPGA
VHDL
ModelSim
Simulations
Firmware
Product Development
Design
Device Drivers
I2C
Fernando Bolanos Summary
Fernando Bolanos, based in Boise, ID, US, is currently a Senior FPGA Designer at Synopsys Inc. Fernando Bolanos brings experience from previous roles at HP and ASCI. Fernando Bolanos holds a 1994 - 1996 M.E. in Electronic Digital Design @ ITESO Universidad Jesuita de Guadalajara. With a robust skill set that includes Cadence Schematic Capture, Hardware Architecture, Digital Electronics, Linux, Perl and more. Fernando Bolanos has 1 emails and 1 mobile phone numbers on RocketReach.
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