Fei Ren Email & Phone Number
Architect and Senior Design Manager @ Synopsys Inc
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Fei Ren Location
- Cupertino, CA, US
Fei Ren Work
- 2025 -now Architect and Senior Design Manager @
- 2022 -2025 Architect and Design Manager @
- 2017 -2021 Staff Design Engineer and Project Lead @
- 2015 -2017 Staff Design Engineer and Verification Lead @
- 2012 -2015 Senior Design and Verification Engineer @
- 2011 -2011 Hardware Engineer Internship @
- 2006 -2011 Research Assistant @
Fei Ren Education
- Missouri University of Science and Technology (Formerly University of Missouri-Rolla)
Ph.D (Electrical Engineering; Hardware Design, Wireless Communications)
2008-2011 - Missouri University of Science and Technology
M.S (Electrical Engineering; Embedded System, Wireless Communications)
2006-2007 - University of Electronic Science and Technology of China
B.S (Electrical Engineering: Embedded System, Wireless Communications)
2001-2006
Fei Ren Skills
- system verilog
- uvm
- ovm
- c++
- FPGA
- Verilog
- VHDL
- ASIC
- Debugging
- Digital Signal Processors
- SoC
- ModelSim
- Embedded Software
- Integrated Circuit Design
- IC
- Design
- Intel
- Technology
- Education
- Science
Fei Ren Summary
- Fei Ren, based in Cupertino, CA, US, is currently a Architect and Senior Design Manager at Synopsys Inc. Fei Ren brings experience from previous roles at Synopsys Inc and Marvell Semiconductor. Fei Ren holds a 2008 - 2011 Ph.D in Electrical Engineering; Hardware Design, Wireless Communications @ Missouri University of Science and Technology (Formerly University of Missouri-Rolla). With a robust skill set that includes system verilog, uvm, ovm, c++, FPGA and more. Fei Ren has 2 emails and 1 mobile phone numbers on RocketReach.
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