Esha Agarwal Email & Phone Number
Integration Lead @ Apple
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Esha Agarwal Location
- Cupertino, CA, US
Esha Agarwal Work
- 2022 -now Integration Lead @
- 2019 -2023 Senior Pixel IP Design Engineer @
- 2017 -2019 Senior Circuit Design Engineer @
- 2013 -2017 Circuit Design Engineer @
- 2012 -2012 Circuit Design Intern @
- 2010 -2011 SoC Design Engineer @
- 2009 -2010 Design Engineer @
- 2009 -2009 Intern @
Esha Agarwal Education
- University of California, Los Angeles
Master of Science (M.S.) (Electrical and Electronics Engineering)
2011-2013 - Manipal Institute of Technology
Bachelor of Engineering (BE) (Electrical, Electronics and Communications Engineering)
2005-2009
Esha Agarwal Skills
- Verilog
- Analog Circuit Design
- RTL design
- Cadence Virtuoso
- Circuit Design
- VHDL
- ModelSim
- RTL coding
- FPGA
- Semiconductors
- SPICE
- Matlab
- C++
- TCL
- Logic Synthesis
- Parasitic Extraction
- SoC
- Computer Hardware
- CMOS
- DRC
- Design
Esha Agarwal Summary
- Esha Agarwal, based in Cupertino, CA, US, is currently a Integration Lead at Apple. Esha Agarwal brings experience from previous roles at Apple. Esha Agarwal holds a 2011 - 2013 Master of Science (M.S.) in Electrical and Electronics Engineering @ University of California, Los Angeles. With a robust skill set that includes Verilog, Analog Circuit Design, RTL design, Cadence Virtuoso, Circuit Design and more. Esha Agarwal has 2 emails and 1 mobile phone numbers on RocketReach.
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