Esha Agarwal Email & Phone Number
Integration Lead @ Apple
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Esha Agarwal Location
- Cupertino, CA, US
Esha Agarwal Work
- Integration Lead @ (October 2022 - Present)
- Senior Pixel IP Design Engineer @ (January 2019 - June 2023)
- Senior Circuit Design Engineer @ (September 2017 - January 2019)
- Circuit Design Engineer @ (April 2013 - September 2017)
- Circuit Design Intern @ (June 2012 - September 2012)
- SoC Design Engineer @ (February 2010 - August 2011)
- Design Engineer @ (September 2009 - February 2010)
- Intern @ (January 2009 - July 2009)
Esha Agarwal Education
- UCLA
Master of Science (M.S.) (Electrical and Electronics Engineering)
2011-2013 - Manipal Institute of Technology
Bachelor of Engineering (BE) (Electrical, Electronics and Communications Engineering)
2005-2009
Esha Agarwal Skills
- Analog Circuit Design
- C++
- CMOS
- Cadence Virtuoso
- Circuit Design
- DRC
- FPGA
- Logic Synthesis
- Matlab
- ModelSim
- Parasitic Extraction
- RTL Design
- RTL coding
- SPICE
- Semiconductors
- SoC
- TCL
- VHDL
- Verilog
- Computer Hardware
- Design
Esha Agarwal Summary
- Esha Agarwal, based in Cupertino, CA, US, is currently a Integration Lead at Apple. Esha Agarwal brings experience from previous roles at Apple. Esha Agarwal holds a 2011 - 2013 Master of Science (M.S.) in Electrical and Electronics Engineering @ UCLA. With a robust skill set that includes Analog Circuit Design, C++, CMOS, Cadence Virtuoso, Circuit Design and more. Esha Agarwal has 2 emails and 1 mobile phone numbers on RocketReach.
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