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Eric Shiu Location
Santa Clara, CA, US
Eric Shiu Work
2021 -now Memory archiect and technologist @
2021 -now Hardware Engineer @
2020 -2021 Board Member @
2017 -2021 Technologist, Consumer Hw @
2014 -2017 Chip Lead, Consumer Hw @
2010 -2014 Soc Design Lead @
2008 -2010 Engineering Manager @
2004 -2008 Principal Engineer and Engineering Manager @
2004 -2004 Staff Engineer @
1998 -2004 Member of Technical Staff @
1994 -1996 Electronic Ensign @ Roc Navy Logistics Cammand
Eric Shiu Education
Stanford University
Master Of Science
1996-1998
National Chiao Tung University
Bachelor Of Science
1990-1994
Eric Shiu Skills
SoC
ASIC
VLSI
Microprocessors
EDA
Verilog
IC
RTL design
Hardware Architecture
Semiconductors
Physical Design
Computer Architecture
SystemVerilog
Debugging
Processors
Circuit Design
Electronics
FPGA
Low-power Design
ARM
Static Timing Analysis
TCL
Logic Design
Analog
Digital Signal Processors
Mixed Signal
System on a Chip (SoC)
CMOS
Application-Specific Integrated Circuits (ASIC)
Field-Programmable Gate Arrays (FPGA)
Very-Large-Scale Integration (VLSI)
Field Programmable Gate Arrays Fpga
System On A Chip Soc
Application Specific Integrated Circuits Asic
Low Power Design
Very Large Scale Integration Vlsi
Digital Signal
System on a Chip
Very Large Scale Integration
Application Specific Integrated Circuits
Field Programmable Gate Arrays
Eric Shiu Summary
Eric Shiu, based in Santa Clara, CA, US, is currently a Memory archiect and technologist at Rivos. Eric Shiu brings experience from previous roles at Rivo, Jedec Solid State Technology Association and Google. Eric Shiu holds a 1996 - 1998 Master Of Science @ Stanford University. With a robust skill set that includes SoC, ASIC, VLSI, Microprocessors, EDA and more. Eric Shiu has 3 emails and 3 mobile phone numbers on RocketReach.
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