Eric Chiou Email & Phone Number
Design Engineer @ Intel Corporation
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Eric Chiou Location
- San Jose, CA, US
Eric Chiou Work
- Design Engineer @ (October 2016 - Present)
- Senior Member Technical Staff @ Altera (December 2013 - October 2016)
- Sr. Physical Design Manager @ (May 2012 - December 2013)
- Staff design engineer @ (April 2010 - May 2012)
- senior design Engineer @ (April 1998 - April 2010)
Eric Chiou Education
- University of Southern California
MS (Engineer)
1996-1998 - NCKU
Bachelor of Science (BS) (Physics)
1990-1994
Eric Chiou Skills
- Simulations
- Physical Design
- Design
- ASIC
- Timing
- Static Timing Analysis
- Floorplanning
- Low Power Design
- VLSI
- Clock Tree Synthesis
- SRAM
- EDA
- Simulation
- Timing Closure
Eric Chiou Summary
- Eric Chiou, based in San Jose, CA, US, is currently a Design Engineer at Intel Corporation. Eric Chiou brings experience from previous roles at Altera and IDT. Eric Chiou holds a 1996 - 1998 MS in Engineer @ University of Southern California. With a robust skill set that includes Simulations, Physical Design, Design, ASIC, Timing and more. Eric Chiou has 4 emails and 4 mobile phone numbers on RocketReach.
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