Verification Tools Engineer @ (June 2019 - January 2021)
Pre-silicon Verification Engineer @ (April 2018 - June 2019)
Power Validation Engineer @ (November 2014 - April 2018)
Graduate Student @ (August 2013 - July 2014)
Digital System Design Consultant @ (May 2013 - August 2013)
Graduate Intern @ (March 2012 - August 2012)
Digital Engineering Co-op @ L-3 Communications Nova Engineering (June 2011 - September 2011)
Digital Engineering Co-op @ L-3 Communications Nova Engineering (January 2011 - March 2011)
Eric Carver Education
University of Cincinnati
Master of Science (MS) (Computer Engineering)
2009-2014
University of Cincinnati
Bachelor of Science (BS) (Electrical Engineering)
2009-2014
Eric Carver Skills
ASIC
Algorithm Design
C
C++
CVS
Computer Architecture
Debugging
FEC
FPGA
FPGA prototyping
Fine-grained Parallelism
Git
Infiniband
Kernel Debugging
LaTeX
Linux
Open Verification Methodology
Optimization
PCIe
Parallel Computing
Perl
Python
RDMA over Converged Ethernet
Rapid Prototyping
Regular Expressions
Shell Scripting
Signal Processing
SoC
Subversion
SystemVerilog
Technical Writing
Universal Verification Methodology (UVM)
VHDL
Validation Strategy
Verilog
Eric Carver Summary
Eric Carver, based in Denver, CO, US, is currently a Staff Verification Engineer at Intel Corporation. Eric Carver brings experience from previous roles at Intel Corporation and University of Cincinnati. Eric Carver holds a 2009 - 2014 Master of Science (MS) in Computer Engineering @ University of Cincinnati. With a robust skill set that includes ASIC, Algorithm Design, C, C++, CVS and more. Eric Carver has 4 emails on RocketReach.
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