Ellen Chiu Email & Phone Number
Senior Layout Designer @ Intel Corporation
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Ellen Chiu Location
- Saratoga, CA, US
Ellen Chiu Work
- Senior Layout Designer @ (August 2008 - Present)
- Staff Layout Designer @ (January 2006 - July 2008)
- MTS @ Matrix Semiconductor (January 2001 - January 2006)
- Layout Designer @ Altera (June 1999 - April 2001)
- Layout Designer @ (August 1996 - June 1998)
Ellen Chiu Education
- University of Illinois Urbana-Champaign
Master of Science - MS (Department of Physiology and Biophysics)
- National Taiwan University
Bachelor of Science - BS (Department of Zoology)
- Silicon Drafting Institute
certification (CMOS/BiCMOS Layout)
Ellen Chiu Skills
- Analog Circuit Design
- Antennas
- CMOS
- Cadence
- Cadence Virtuoso
- Calibre
- Debugging
- Design Rule Checking (DRC)
- Floor Plans
- Hercules
- High Voltage
- IC
- IC layout
- ICM
- IO
- Integration
- LVS
- Mixed Signal
- Phase-Locked Loop (PLL)
- RV
- Redhawk
- Semiconductors
- SoC
- Synopsys IC Compiler
- dfm
- ASIC
Ellen Chiu Summary
- Ellen Chiu, based in Saratoga, CA, US, is currently a Senior Layout Designer at Intel. Ellen Chiu brings experience from previous roles at SanDisk, Matrix Semiconductor, Altera and Intel. Ellen Chiu holds a Master of Science - MS in Department of Physiology and Biophysics @ University of Illinois Urbana-Champaign. With a robust skill set that includes Analog Circuit Design, Antennas, CMOS, Cadence, Cadence Virtuoso and more. Ellen Chiu has 1 emails and 1 mobile phone numbers on RocketReach.
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