Edward Yang Email & Phone Number
Vice President, Architecture Validation and Design Verification @ VeriSilicon Holdings Co., Ltd.
5 free lookup(s).
Edward Yang Location
- San Jose, CA, US
Edward Yang Work
- 2015 - now Vice President, Architecture Validation and Design Verification @
- 2018 - now General Manager, US Operation @ Denglin Technology
- 2014 - 2015 Director, Architecture Validation and Design Verification @
- 2008 - 2014 Manager, Design and Verification and Fpga Validation @
- 2006 - 2008 Staff Engineer @
- 2001 - 2006 MTS @
- 1997 - 2000 Senior Design Engineer @
Edward Yang Education
- Santa Clara University
Master Of Science
1996 - 1997
Edward Yang Skills
- Schedule Planning
- RTL Development
- Ethernet
- ASIC
- VHDL
- SoC
- Semiconductors
- RTL design
- FPGA
- Metro Ethernet
- EDA
- IC
- VLSI
- Integrated Circuit Design
- Device Drivers
- Routers
- Debugging
- SystemVerilog
- Verilog
- TCL
Edward Yang Summary
- Edward Yang, based in San Jose, CA, US, is currently a Vice President, Architecture Validation and Design Verification at Verisilicon Holdings Co., Ltd.. Edward Yang brings experience from previous roles at Denglin Technology, Vivante Corporation and Juniper Networks. Edward Yang holds a 1996 - 1997 Master Of Science @ Santa Clara University. With a robust skill set that includes Schedule Planning, RTL Development, Ethernet, ASIC, VHDL and more. Edward Yang has 2 emails on RocketReach.
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Top VeriSilicon Holdings Co., Ltd. Employees
Yanjun Zhang
VP of Software Development
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Kainan Cha
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