Edward Yang Email & Phone Number
Vice President, Architecture Validation and Design Verification @ VeriSilicon Holdings Co., Ltd.
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Edward Yang Location
- San Jose, CA, US
Edward Yang Work
- Vice President, Architecture Validation and Design Verification @ (October 2015 - Present)
- General Manager, US Operation @ Denglin Technology (August 2018 - Present)
- Director, Architecture Validation and Design Verification @ (August 2014 - October 2015)
- Manager, Design and Verification and Fpga Validation @ (August 2008 - August 2014)
- Staff Engineer @ (May 2006 - July 2008)
- MTS @ (February 2001 - February 2006)
- Senior Design Engineer @ (July 1997 - September 2000)
Edward Yang Education
- Santa Clara University
Master Of Science
1996-1997
Edward Yang Skills
- Schedule Planning
- RTL Development
- Ethernet
- ASIC
- VHDL
- SoC
- Semiconductors
- RTL design
- FPGA
- Metro Ethernet
- EDA
- IC
- VLSI
- Integrated Circuit Design
- Device Drivers
- Routers
- Debugging
- SystemVerilog
- Verilog
- TCL
Edward Yang Summary
- Edward Yang, based in San Jose, CA, US, is currently a Vice President, Architecture Validation and Design Verification at Verisilicon Holdings Co., Ltd.. Edward Yang brings experience from previous roles at Denglin Technology, Vivante Corporation and Juniper Networks. Edward Yang holds a 1996 - 1997 Master Of Science @ Santa Clara University. With a robust skill set that includes Schedule Planning, RTL Development, Ethernet, ASIC, VHDL and more. Edward Yang has 1 emails and 1 mobile phone numbers on RocketReach.
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