Ed Nolan Email & Phone Number
Digital ASIC Verification Lead @ Analog Devices
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Ed Nolan Location
- Lake Oswego, OR, US
Ed Nolan Work
- Digital ASIC Verification Lead @ (September 2022 - Present)
- ASIC and FPGA Verification Engineer @ (August 2007 - August 2022)
- Digital IP development engineer @ (January 2004 - January 2007)
- ASIC design and verification consultant @ Digital Analytics, LLC (Owner) (January 1997 - January 2004)
- ASIC Design Engineer @ (June 1995 - November 1997)
- ASIC Design Engineer @ (January 1990 - January 1995)
Ed Nolan Education
- Arizona State University
bsee (engineering)
1986-1990
Ed Nolan Skills
- SystemVerilog
- Semiconductors
- PCIe
- Hardware Architecture
- ASIC
- SystemC
- UVM
- Italian Language
- FPGA
- SoC
- Verilog
- NCSim
- EDA
- C++
- Specman
- Hardware
- Functional Verification
- RTL design
Ed Nolan Summary
- Ed Nolan, based in Lake Oswego, OR, US, is currently a Digital ASIC Verification Lead at Analog Devices. Ed Nolan brings experience from previous roles at Teradyne, Synopsys, Digital Analytics, LLC (Owner) and Motorola Solutions. Ed Nolan holds a 1986 - 1990 bsee in engineering @ Arizona State University. With a robust skill set that includes SystemVerilog, Semiconductors, PCIe, Hardware Architecture, ASIC and more. Ed Nolan has 1 emails and 2 mobile phone numbers on RocketReach.
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