Dixesh Patel's Location
New York, United States
Dixesh Patel's Work
- Design Verification Engineer @ Rambus
- Design and Verification Engineer @ Atria Logic Inc.
- Internship @ Maven Silicon
Dixesh Patel's Education
- PARUL INSTITUTE OF ENGG. AND TECH., LIMDA, VAGHODIA 037
Master of Engineering (MEng) (Electrical, Electronics and Communications Engineering)
2013 - 2015 - Sigma Institute of Engineering (SFI) -Barrrol-Ta:Waghodiya Di:Vadodara. 775
Bachelor’s Degree (Electronic and Communications Engineering)
2009 - 2013
Dixesh Patel's Skills
- SystemVerilog
- Sta
- Application Specific Integrated Circuits Asic
- Field Programmable Gate Arrays Fpga
- Verilog
- Very Large Scale Integration Vlsi
- Digital Designs
- Universal Verification Methodology Uvm
- Very Large Scale Integration
- Application Specific Integrated Circuits
Dixesh Patel's Summary
Dixesh Patel, based in New York, United States, is currently a Design Verification Engineer at Rambus, bringing experience from previous roles at Atria Logic Inc. and Maven Silicon. Dixesh Patel holds a 2013 - 2015 Master of Engineering (MEng) in Electrical, Electronics and Communications Engineering @ PARUL INSTITUTE OF ENGG. AND TECH., LIMDA, VAGHODIA 037. With a robust skill set that includes SystemVerilog, Sta, Application Specific Integrated Circuits Asic, Field Programmable Gate Arrays Fpga, Verilog and more, Dixesh Patel contributes valuable insights to the industry. Dixesh Patel has 2 emails on RocketReach.
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