Divyang Patel Email & Phone Number
Sr. Manager, Cellular SoC @ Apple
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Divyang Patel Location
- Cupertino, CA, US
Divyang Patel Work
- Sr. Manager, Cellular SoC @ (March 2018 - Present)
Divyang Patel Education
- Arizona State University
MSE (Electrical Engineering, VLSI Design)
1997-1998 - Gujarat University
Bachelor of Engineering (B.E.) (Electronics and Communication)
1992-1996 - A. G. High School
- Sheth C N Vidhayalaya
Divyang Patel Skills
- ASIC
- ASIC Timing Engineer
- Application-Specific Integrated Circuits (ASIC)
- Clock Tree Synthesis
- Logic Synthesis
- Low-power Design
- Mixed Signal
- Perl
- Physical Design
- Primetime
- STA
- Semiconductors
- SoC
- Static Timing Analysis
- Synopsys Primetime
- TCL
- Timing Closure
- VLSI
- backend design
- Application Specific Integrated Circuits Asic
- Low Power Design
- Computer Hardware
- Application Specific Integrated Circuits
Divyang Patel Summary
- Divyang Patel, based in Cupertino, CA, US, is currently a Sr. Manager, Cellular SoC at Apple. Divyang Patel holds a 1997 - 1998 MSE in Electrical Engineering, VLSI Design @ Arizona State University. With a robust skill set that includes ASIC, ASIC Timing Engineer, Application-Specific Integrated Circuits (ASIC), Clock Tree Synthesis, Logic Synthesis and more. Divyang Patel has 2 emails and 1 mobile phone numbers on RocketReach.
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