Divyang Patel Location
- Cupertino, CA, US
Divyang Patel Work
- 2018 - now Sr. Manager, Cellular SoC @
- 2013 - 2018 STA Engineer @
- 2010 - 2013 Staff ASIC Physical Design Engineer, Static Timing Analysis @
- 2008 - 2010 Sr. ASIC Physical Design Engineer @
- 2006 - 2008 Sr. Graphics Hardware Engineer @
- 1998 - 2008 Sr. Component Design Engineer @
Divyang Patel Education
- Arizona State University
MSE, Electrical Engineering (VLSI Design)
1997 - 1998 - Gujarat University
Bachelor of Engineering (B.E.) (Electronics and Communication)
1992 - 1996 - A. G. High School
- Sheth C N Vidhayalaya
- null
Divyang Patel Skills
- Static Timing Analysis
- ASIC
- Physical Design
- Synopsys Primetime
- Clock Tree Synthesis
- TCL
- Perl
- ASIC Timing Engineer
- backend design
- STA
- Logic Synthesis
- Timing Closure
- Mixed Signal
- Primetime
- SoC
- Low-power Design
- VLSI
- Semiconductors
- Application Specific Integrated Circuits Asic
- Low Power Design
- Computer Hardware
- Application Specific Integrated Circuits
Divyang Patel Summary
- Divyang Patel, based in Cupertino, CA, US, is currently a Sr. Manager, Cellular SoC at Apple. Divyang Patel brings experience from previous roles at Apple and Intel Corporation. Divyang Patel holds a 1997 - 1998 MSE, Electrical Engineering in VLSI Design @ Arizona State University. With a robust skill set that includes Static Timing Analysis, ASIC, Physical Design, Synopsys Primetime, Clock Tree Synthesis and more. Divyang Patel has 1 emails and 2 mobile phone numbers on RocketReach.
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