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Dipal Shah Location
Santa Clara, CA, US
Dipal Shah Work
2026 -now Director, ASIC Design-For-Test @
2025 -now ASIC Architect and Engineering Leader @
2023 -2025 Sr. Director - Engineering @
2018 -2023 Principal Engineer @
2005 -2018 DFT-lead Engineer @
2002 -2005 DFT Engineer @
2001 -2002 Technical Marketing Engineer - DFT @
Dipal Shah Education
Portland State University
Doctor of Philosophy (PhD) (Electrical and Computer Engineering)
Dipal Shah Skills
Mixed Signal
Tetramax
Debugging
JTAG
Static Timing Analysis
Primetime
Analog
Formal Verification
Xilinx
RTL design
NCSim
DFT
Processors
VLSI
ASIC
Digital Signal Processors
Semiconductors
SoC
Verilog
EDA
IC
SystemVerilog
Computer Architecture
Perl
VHDL
FPGA
Microprocessors
Very-Large-Scale Integration (VLSI)
Application-Specific Integrated Circuits (ASIC)
System on a Chip (SoC)
Field-Programmable Gate Arrays (FPGA)
Field Programmable Gate Arrays Fpga
System On A Chip Soc
Intel
Program Management
Testing
Application Specific Integrated Circuits Asic
SQL
Very Large Scale Integration Vlsi
Engineering
Java
Marketing Strategy
Microsoft Office
Very Large Scale Integration
Application Specific Integrated Circuits
System on a Chip
Field Programmable Gate Arrays
Dipal Shah Summary
Dipal Shah, based in Santa Clara, CA, US, is currently a Director, ASIC Design-For-Test at Cisco. Dipal Shah brings experience from previous roles at Cisco, Northrop Grumman, Broadcom Inc. and Intel corporation. Dipal Shah holds a Doctor of Philosophy (PhD) in Electrical and Computer Engineering @ Portland State University. With a robust skill set that includes Mixed Signal, Tetramax, Debugging, JTAG, Static Timing Analysis and more. Dipal Shah has 1 emails and 3 mobile phone numbers on RocketReach.
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