Staff Design Automation and Physical Design Engineer @ (August 2010 - July 2013)
Analog-Mixed Signal Methodology Services Engineer @ (January 2008 - August 2010)
Mixed Signal CAD Intern @ (May 2007 - August 2007)
Intern @ (January 2005 - May 2005)
Dipal Patel Education
Syracuse University
M.S. (Computer Engineering / Hardware Track)
2006-2007
Gujarat University
B.E. (Electronics & Communication)
2001-2005
Dipal Patel Skills
Development
Cadence Skill
Power
Cadence Virtuoso
Physical Verification
Perl
Sta
Spectre
CAD
Verilog
Integrated Circuit Design
Cadence
Engineering
TCL
Cadence Encounter
Pdk
Integrated Circuit
Verilog Ams
Mixed Signal
Ams Simulation
CMOS
LVS
EDA
C++
Primetime
Timing Closure
Python
Open Access
Semiconductors
Physical Design
Design
Static Timing Analysis
Software Development
Power Analysis
Analysis
Verification
Shell Scripting
IC
Dipal Patel Summary
Dipal Patel, based in San Jose, CA, US, is currently a Technical Program Manager- ASIC (Common Hardware Group) at Cisco. Dipal Patel brings experience from previous roles at Intel Corporation, Flex Logix Technologies, Inc. and AMD. Dipal Patel holds a 2006 - 2007 M.S. in Computer Engineering / Hardware Track @ Syracuse University. With a robust skill set that includes Development, Cadence Skill, Power, Cadence Virtuoso, Physical Verification and more. Dipal Patel has 2 emails and 2 mobile phone numbers on RocketReach.
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