Dinesh Patil's Location
Fremont, CA, US
Dinesh Patil's Work
- SoC Architect @ Facebook
- Principal Engineer @ Intel Corporation
- Analog Design Manager @ Intel Corporation
- Principal Design Engineer @ Altera
- Technical Director @ MegaChips Corporation
- Design Manager @ Rambus
- Senior member of technical staff @ Rambus
- Member of technical staff @ Sun Microsystems
Dinesh Patil's Education
- Stanford University
PhD (Electrical Engineering)
2002 - 2007 - Indian Institute of Technology, Bombay
B. Tech (EE)
1997 - 2001
Dinesh Patil's Skills
- Memory
- Technology
- Logic Design
- Debugging
- Graphic Design
- Perl
- Dram Phy
- Interfaces
- Technical Design
- VLSI
Dinesh Patil's Summary
Dinesh Patil, based in Fremont, CA, US, is currently a SoC Architect at Facebook, bringing experience from previous roles at Intel Corporation, Altera and Megachips-Corporation. Dinesh Patil holds a 2002 - 2007 PhD in Electrical Engineering @ Stanford University. With a robust skill set that includes Memory, Technology, Logic Design, Debugging, Graphic Design and more, Dinesh Patil contributes valuable insights to the industry. Dinesh Patil has 4 emails and 1 mobile phone number on RocketReach.
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