Principal Package Integration Engineer @ (January 2021 - September 2022)
Principle Package Process Integration Engineer @ (June 2013 - December 2020)
Senior Engineer @ (June 2008 - June 2013)
Engineer @ (August 2005 - June 2008)
Devin Wu Education
National Tsing Hua University
Master of Science (MS) (Engineering and System Science)
2000-2002
Devin Wu Skills
Solder formation by printing and pasting
Wafer bumping processes integration
Dielectric film formation
Semiconductor Industry
Design of Experiments
Failure Analysis
CVD
PVD
Plating
E-less plating
E Less Plating
Devin Wu Summary
Devin Wu, based in Taiwan, is currently a PMTS Packaging Engineer at AMD. Devin Wu brings experience from previous roles at TSMC. Devin Wu holds a 2000 - 2002 Master of Science (MS) in Engineering and System Science @ National Tsing Hua University. With a robust skill set that includes Solder formation by printing and pasting, Wafer bumping processes integration, Dielectric film formation, Semiconductor Industry, Design of Experiments and more. Devin Wu has 1 emails on RocketReach.
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