Dev Desai Email & Phone Number
Senior Hardware Design Engineer @ Microsoft
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Dev Desai Location
- Kirkland, WA, US
Dev Desai Work
- 2020 -now Senior Hardware Design Engineer @
- 2018 -2020 Hardware Development Engineer @
- 2018 -2018 Member Of Technical Staff @
- 2018 -2018 ASIC Design Engineer @ Scalable Systems Research Labs Inc.
- 2017 -2017 Application Engineer Intern @
- 2013 -2013 Summer Trainee @
Dev Desai Education
- San Jose State University
Master of Science (MS) (Electrical and Electronics Engineering)
2015-2017 - Gujarat Technological University, Ahmedbabd
Bachelor of Engineering (B.E.) (Electronics Engineering)
2010-2014
Dev Desai Skills
- Semiconductor Device
- Altera Quartus
- PowerPoint
- Cadence Virtuoso
- Computer Architecture
- Field Programmable Gate Arrays Fpga
- C
- System Verilog
- Logic Synthesis
- Perl
- Microsoft PowerPoint
- Matlab
- Microsoft Azure
- Image Processing
- Place And Route
- Verilog
- Design Verification Testing
- HTML
- Programming
- Microsoft Office
- Microsoft Word
- Nios Ii
- Microsoft Excel
- RTL coding
- VHDL
- C++
- ModelSim
- Universal Verification Methodology Uvm
- Digital Signal Processing
- Python
- SystemVerilog
- Management
- Synopsys tools
- Hdlc
- Research
- Cisco Routers
- Static Timing Analysis
- Very Large Scale Integration Vlsi
- Ethernet Sw
- RTL verification
- Universal Verification Methodology
- Very Large Scale Integration
- Field Programmable Gate Arrays
Dev Desai Summary
- Dev Desai, based in Kirkland, WA, US, is currently a Senior Hardware Design Engineer at Microsoft. Dev Desai brings experience from previous roles at Microsoft, Chelsio Communications, Scalable Systems Research Labs Inc. and QuickLogic. Dev Desai holds a 2015 - 2017 Master of Science (MS) in Electrical and Electronics Engineering @ San Jose State University. With a robust skill set that includes Semiconductor Device, Altera Quartus, PowerPoint, Cadence Virtuoso, Computer Architecture and more. Dev Desai has 3 emails and 6 mobile phone numbers on RocketReach.
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