Deepana Patel Email
Technical Manager and Architect @ VeriFast Technologies
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Deepana Patel Location
- Ahmedabad, GJ, IN
Deepana Patel Work
- Technical Manager and Architect @ (April 2023 - Present)
- Entrepreneur @ Self-employed (August 2021 - March 2023)
- Sr. ASIC Design Engineer @ (October 2018 - July 2021)
- Verification Lead @ SeviTech Systems Pvt. Ltd. (December 2016 - August 2018)
- Senior ASIC Verification Engineer-L2 @ (February 2012 - October 2016)
Deepana Patel Education
- Ganpat University
Bachelor of Technology - BTech (Electronics and Communication Engineering)
2006-2010
Deepana Patel Skills
- AMBA AHB
- AMBA APB
- AXI
- AXI Stream
- AccuRev
- Application-Specific Integrated Circuits (ASIC)
- C
- C++
- CVS
- Display Port
- Embedded Display Port
- Field-Programmable Gate Arrays (FPGA)
- Functional Verification
- GIT
- Gate Level Simulation
- HDMI
- I2C
- Java
- LPDDR3
- Linux
- MIPI DPHY
- MIPI MPHY
- MIPI-CSI
- MIPI-DSI
- MySQL
- NCSim
- Object-Oriented Programming (OOP)
- PCI Express
- PWM
- Perforce
- Perl
- SPI
- SVN
- System Verilog
- UFS 3.0
- UPI
- Unipro
- Universal Asynchronous Receiver/Transmitter (UART)
- Universal Verification Methodology (UVM)
- VCS
- Verilog
- Verilog HDL
- Very-Large-Scale Integration (VLSI)
- eMMC 5.1
Deepana Patel Summary
- Deepana Patel, based in Ahmedabad, GJ, IN, is currently a Technical Manager and Architect at VeriFast Technologies. Deepana Patel brings experience from previous roles at Self-employed, Infinera, SeviTech Systems Pvt. Ltd. and eInfochips. Deepana Patel holds a 2006 - 2010 Bachelor of Technology - BTech in Electronics and Communication Engineering @ Ganpat University. With a robust skill set that includes AMBA AHB, AMBA APB, AXI, AXI Stream, AccuRev and more. Deepana Patel has 1 emails on RocketReach.
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