David Neves Email
Senior Manager, IC Design and Principal Engineer @ Silicon Labs
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David Neves Location
- Rennes, FR
David Neves Work
- 2024 -now Senior Manager, IC Design and Principal Engineer @
- 2022 -2024 Principal Design Engineer @
- 2010 -2022 Senior Design Engineer @
- 2008 -2010 Design Engineer @
- 2005 -2008 Digital Design Engineer @ Integration Associates, Inc.
- 2003 -2005 Hardware Developer @
David Neves Education
- Instituto Superior Técnico
Post graduate course (Advanced Microelectronics Engineering)
2002-2003 - Instituto Superior Técnico
Licenciatura (Engenharia Electrotécnica)
1995-2002 - EPPET - Escola Profissional Pública de Electrónica e Telecomunicações
Technical Course (Electronics and Telecommunications)
1992-1995
David Neves Skills
- RTL design
- VHDL
- Simulations
- FPGA
- Semiconductors
- Integrated Circuit Design
- Verilog
- ASIC
- Hardware
- IC
- SystemVerilog
- Functional Verification
- Programmable Logic
- ATPG
- Mixed Signal
- Logic Synthesis
- Perl
- TCL
- EDA
- Verilog-AMS
- Semiconductor Design
- Place & Route
- Static Timing Analysis
- Verilog-A
- DFT
- BIST
- Hardware Verification
- Hardware Development
- CMOS
- Place And Route
- Verilog Ams
David Neves Summary
- David Neves, based in Rennes, FR, is currently a Senior Manager, IC Design and Principal Engineer at Silicon Labs. David Neves brings experience from previous roles at Silicon Labs and Integration Associates, Inc.. David Neves holds a 2002 - 2003 Post graduate course in Advanced Microelectronics Engineering @ Instituto Superior Técnico. With a robust skill set that includes RTL design, VHDL, Simulations, FPGA, Semiconductors and more. David Neves has 2 emails on RocketReach.
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