David Aceves Email & Phone Number
Senior Design Verification Engineer @ Everspin Technologies
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David Aceves Location
- Austin, TX, US
David Aceves Work
- Senior Design Verification Engineer @ (April 2021 - Present)
- Design Verification Engineer @ (March 2018 - October 2018)
- Design Verification Engineer @ NXP (Formerly Freescale and Motorola) (October 2000 - July 2016)
- Design and Verification Engineer @ (January 1997 - January 2000)
David Aceves Education
- The University of Texas at San Antonio
Bachelor’s Degree (Electrical and Electronics Engineering)
David Aceves Skills
- Application-Specific Integrated Circuits (ASIC)
- CPF
- Cadence
- ClearCase
- Code Coverage
- Debugging
- DesignSync
- Engineering
- Functional Verification
- Gate Level Simulation
- Low-power Design
- Microcontrollers
- Microsoft Excel
- Microsoft Office
- Microsoft Word
- Mixed-Signal IC Design
- Module Development
- NC-Verilog
- Perl
- RTL Verification
- Semiconductors
- Simulations
- System on a Chip (SoC)
- SystemVerilog
- TCL
- Universal Verification Methodology (UVM)
- Verilog
- Verilog-AMS
David Aceves Summary
- David Aceves, based in Austin, TX, US, is currently a Senior Design Verification Engineer at Everspin Technologies. David Aceves brings experience from previous roles at Sankalp Semiconductor, NXP (Formerly Freescale and Motorola) and Eureka Software. David Aceves holds a Bachelor’s Degree in Electrical and Electronics Engineering @ The University of Texas at San Antonio. With a robust skill set that includes Application-Specific Integrated Circuits (ASIC), CPF, Cadence, ClearCase, Code Coverage and more. David Aceves has 1 emails and 1 mobile phone numbers on RocketReach.
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Top Everspin Technologies Employees
Bill Cooper
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Dave Schrenk
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Sean Dougherty
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Marna Dahan
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Tony Suzer
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Charles Husted
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Sanjeev Aggarwal
President and Chief Executive Officer
Scottsdale, AZ, US
Chuck Bohac
Director, Strategic Business Development
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Kerry Nagel
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Radha Sadhu
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