Danilo Gerna Email & Phone Number
Principal Design Engineer @ Power Integrations
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Danilo Gerna Location
- Biel/Bienne, BE, CH
Danilo Gerna Work
- Principal Design Engineer @ (April 2026 - Present)
- Senior Staff IC Design Engineer @ (October 2023 - Present)
- Senior Staff Design Engineer @ (October 2021 - September 2023)
- Senior analog engineer team lead @ (November 2015 - October 2021)
- Senior Analog Design Engineer TPMS Technical Lead @ (January 2018 - September 2021)
- Principal Engineer @ (March 2014 - October 2015)
- Senior Staff Engineer @ (August 2008 - February 2014)
- Principal Engineer at nemeriX @ (October 2005 - July 2008)
- Sr. Engineering Manager @ Newlogic (July 2004 - September 2005)
- Principal Engineer @ New Logic Technology (January 2002 - June 2004)
- Senior Engineer @ (October 1998 - December 2001)
- Visiting Industrial Fellow @ (June 1997 - September 1998)
Danilo Gerna Education
- Berkeley College
Danilo Gerna Skills
- SoC
- ASIC
- IC
- Semiconductors
- Analog Circuit Design
- Mixed Signal
- EDA
- Analog
- Electronics
- ARM
- Semiconductor Industry
- Embedded Systems
- CMOS
- Integrated Circuit Design
- Verilog
- RTL design
- Low-power Design
- Embedded Software
- Static Timing Analysis
- Digital Signal Processors
- Debugging
- FPGA
- RF
- Analogue
- Low Power Design
Danilo Gerna Summary
- Danilo Gerna, based in Biel/Bienne, BE, CH, is currently a Principal Design Engineer at Power Integrations. Danilo Gerna brings experience from previous roles at Power Integrations, Knowles Corporation and MELEXIS. Danilo Gerna holds a Berkeley College. With a robust skill set that includes SoC, ASIC, IC, Semiconductors, Analog Circuit Design and more. Danilo Gerna has 2 emails and 2 mobile phone numbers on RocketReach.
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Danilo Gerna
Principal Design Engineer
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