Danilo Gerna Email & Phone Number
Principal Design Engineer @ Power Integrations
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Danilo Gerna Location
- Biel/Bienne, BE, CH
Danilo Gerna Work
- 2026 -now Principal Design Engineer @
- 2023 -now Senior Staff IC Design Engineer @
- 2021 -2023 Senior Staff Design Engineer @
- 2015 -2021 Senior analog engineer team lead @
- 2018 -2021 Senior Analog Design Engineer TPMS Technical Lead @
- 2014 -2015 Principal Engineer @
- 2008 -2014 Senior Staff Engineer @
- 2005 -2008 Principal Engineer at nemeriX @
- 2004 -2005 Sr. Engineering Manager @ Newlogic
- 2002 -2004 Principal Engineer @ New Logic Technology
- 1998 -2001 Senior Engineer @
- 1997 -1998 Visiting Industrial Fellow @
Danilo Gerna Education
- Berkeley College
Danilo Gerna Skills
- SoC
- ASIC
- IC
- Semiconductors
- Analog Circuit Design
- Mixed Signal
- EDA
- Analog
- Electronics
- ARM
- Semiconductor Industry
- Embedded Systems
- CMOS
- Integrated Circuit Design
- Verilog
- RTL design
- Low-power Design
- Embedded Software
- Static Timing Analysis
- Digital Signal Processors
- Debugging
- FPGA
- RF
- Analogue
- Low Power Design
Danilo Gerna Summary
- Danilo Gerna, based in Biel/Bienne, BE, CH, is currently a Principal Design Engineer at Power Integrations. Danilo Gerna brings experience from previous roles at Power Integrations, Knowles Corporation and MELEXIS. With a robust skill set that includes SoC, ASIC, IC, Semiconductors, Analog Circuit Design and more. Danilo Gerna has 2 emails and 2 mobile phone numbers on RocketReach.
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