Senior FPGA Design Engineer @ (October 2023 - June 2024)
Lead FPGA Design Engineer @ Vertex Aerospace (January 2022 - June 2023)
Senior Electrical Engineer @ (March 2019 - July 2022)
Component Test Engineer @ (October 2017 - July 2018)
Project Design Engineer @ (August 2017 - October 2017)
Electrical Engineer - Co-Op @ (January 2011 - December 2014)
Daniel Shafer Education
Texas State University
Bachelor's of Science (Electrical Engineering- Nano and Micro Devices; Applied Mathematics)
2012-2017
Daniel Shafer Skills
.NET Framework
AMD
Advanced CMOS technology
Aerospace
Analog Circuit Design
Application-Specific Integrated Circuits (ASIC)
C#
C++
Clean Rooms
Defense
Digital Circuit Design
Digital Designs
Digital Electronics
Electrical Engineering
Electroceramics
Electronic Engineering
Electronics
Electronics Hardware Design
Embedded Software
Embedded Systems
Engineering
Engineering Design
FPGA
FPGA prototyping
Field-Programmable Gate Arrays (FPGA)
Firmware
Functional Verification
LTSpice
Leadership
Linux
Mentor Graphics
Mentoring
Microcontrollers
Microelectronics
Nanofabrication
Nanotechnology
PCB
Python
Python (Programming Language)
RTL Coding
RTL Design
RTL Verification
Schematic Capture
Semiconductors
Sensors
Signal Integrity
Solid-State Devices
SystemVerilog
Test Equipment
VHDL
Verilog
Xilinx Vivado
Daniel Shafer Summary
Daniel Shafer, based in Indianapolis, IN, US, is currently a Senior Principal Engineer at JRC Integrated Systems. Daniel Shafer brings experience from previous roles at SAIC, Vertex Aerospace and Raytheon. Daniel Shafer holds a 2012 - 2017 Bachelor's of Science in Electrical Engineering- Nano and Micro Devices; Applied Mathematics @ Texas State University. With a robust skill set that includes .NET Framework, AMD, Advanced CMOS technology, Aerospace, Analog Circuit Design and more. Daniel Shafer has 4 emails and 3 mobile phone numbers on RocketReach.
Looking for a different Daniel Shafer?
Find contact details for 700 million professionals.