If you need more lookups,
subscriptions start at $34 USD/month.
Daniel Han Location
San Jose, CA, US
Daniel Han Work
2022 -now Director of Engineering @
2015 -2025 Director of Engineering @
2009 -2010 Senior Design Verification Engineer @
2007 -2009 Senior Design Verification Engineer @
2002 -2007 Staff Design Verification Engineer @
2000 -2002 Senior Hardware Engineer @
1998 -2000 Design Verification Engineer @
Daniel Han Education
Stanford University 1998-2001
University of Colorado Boulder 1994-1998
Daniel Han Skills
SystemVerilog
VMM
Functional Verification
Open Verification Methodology
Verilog
ARM
Xilinx
Perl
FPGA
Veritas Cluster Server
AXI
V&V
RTL design
ASIC
IC
SoC
UVM
Semiconductors
Debugging
EDA
VLSI
Integrated Circuits (IC)
Very-Large-Scale Integration (VLSI)
Application-Specific Integrated Circuits (ASIC)
Field-Programmable Gate Arrays (FPGA)
System on a Chip (SoC)
Open Verification
Field Programmable Gate Arrays Fpga
Engineering
Integrated Circuits Ic
Application Specific Integrated Circuits Asic
Microsoft Excel
Very Large Scale Integration Vlsi
Hardware
Field Programmable Gate Arrays
Integrated Circuits
Very Large Scale Integration
Application Specific Integrated Circuits
Daniel Han Summary
Daniel Han, based in San Jose, CA, US, is currently a Director of Engineering at AMD. Daniel Han brings experience from previous roles at Xilinx, Apple and Novafora. Daniel Han holds a 1998 - 2001 Stanford University. With a robust skill set that includes SystemVerilog, VMM, Functional Verification, Open Verification Methodology, Verilog and more. Daniel Han has 2 emails and 4 mobile phone numbers on RocketReach.
Looking for a different Daniel Han?
Find contact details for 700 million professionals.