FEOL LEAD INTEGRATOR: 7NM BULK FINFET CMOS DEVELOPMENT @ (January 2015 - September 2018)
RMG MODULE INTEGRATOR: 20NM BULK CMOS DEVELOPMENT @ (June 2014 - December 2014)
FEOL MODULE LEAD: 22NM PDSOI CMOS DEVELOPMENT @ (January 2011 - May 2014)
HIGH-K and METAL GATE INTEGRATOR: 32 and 28NM BULK CMOS DEVELOPMENT @ (June 2007 - December 2010)
INLINE DEFECT INSPECTION: 65 and 45NM BULK CMOS DEVELOPMENT @ (June 2006 - May 2007)
CO-OP PROCESS ENGINEER @ Integrated Nano-Technologies (December 2002 - May 2004)
Dan Jaeger Education
Rochester Institute of Technology
MS (Materials Science)
2005-2006
Rochester Institute of Technology
BS (Microelectronic Engineering)
2000-2005
Dan Jaeger Skills
Nanofabrication
Timelines
Semiconductor Process
Semiconductor Physics
Program Management
Technical Engineering
Presentations
Product Management
Project Management
Product Development
Cross-functional Team Leadership
Research
Microsoft Excel
Microsoft PowerPoint
Analytical Skills
Written Communication
Processes Development
Communication
CMOS
Integration
Low-power Design
Semiconductors
Thin Films
Design of Experiments
Characterization
Failure Analysis
IC
Process Engineering
Process Simulation
Semiconductor Industry
Simulations
Statistics
Process Integration
Materials Science
VLSI
Yield
Very-Large-Scale Integration (VLSI)
Integrated Circuits (IC)
Semiconductor Fabrication
Process Control
Lead Development
Problem Solving
Dan Jaeger Summary
Dan Jaeger, based in Albany, NY, US, is currently a PROCESS INTEGRATION, 14NM BULK FINFET DERIVATIVES at GLOBALFOUNDRIES. Dan Jaeger brings experience from previous roles at GLOBALFOUNDRIES and IBM. Dan Jaeger holds a 2005 - 2006 MS in Materials Science @ Rochester Institute of Technology. With a robust skill set that includes Nanofabrication, Timelines, Semiconductor Process, Semiconductor Physics, Program Management and more. Dan Jaeger has 2 emails and 1 mobile phone numbers on RocketReach.
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