Daewook Kim Email & Phone Number
Sr. Staff Design Manager @ Marvell India
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Daewook Kim Location
- Santa Clara, CA, US
Daewook Kim Work
- 2026 -now Sr. Staff Design Manager @
- 2024 -2026 Senior Design Manager @
- 2017 -2024 ASIC Design Engineer and Design Lead @
- 2009 -2017 SoC Design Engineer and Tech Lead @
- 2009 -2009 Sr. Staff ASIC Design Engineer @
- 2006 -2009 Member of Technical Staff Design Engineer @
- 2006 -2006 Senior Logic Design Engineer @
Daewook Kim Education
- University of Minnesota
Ph.D. (Electrical Engineering)
- Hanyang University
B.S. (Electronic Engineering)
- University of Minnesota
M.S. (Electrical Engineering)
Daewook Kim Skills
- Logic Design
- RTL design
- SoC
- Low Power Design
- Functional Verification
- TCL
- Debugging
- VLSI
- Embedded Systems
- Asic Design
- Verification
- Microprocessors
- Validation
- Static Timing Analysis
- Storage
- Semiconductors
- SystemVerilog
- Data Validation
- Research
- Integrated Circuit Design
- VHDL
- Verilog
- Computer Hardware
- Mobile Devices
- IC
- Design
- Integration
- FPGA
- DFT
- SQL
- ASIC
- ModelSim
Daewook Kim Summary
- Daewook Kim, based in Santa Clara, CA, US, is currently a Sr. Staff Design Manager at Marvell Technology. Daewook Kim brings experience from previous roles at XConn Technologies Holdings Inc., Intel Corporation, Marvell Semiconductor and Synaptics Incorporated. Daewook Kim holds a Ph.D. in Electrical Engineering @ University of Minnesota. With a robust skill set that includes Logic Design, RTL design, SoC, Low Power Design, Functional Verification and more. Daewook Kim has 1 emails and 1 mobile phone numbers on RocketReach.
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