ChipDesign B.V. Information

SERVICES: ChipDesign B.V. is a Belgian IC design house (founded 2012, VAT BE0501.767.340) delivering front-to-back analog mixed-signal and RF / millimeter-wave (mmW) integrated-circuit design services. We design ASICs in silicon-based triple-well bulk and twin-well PD- and FD-SOI CMOS, BCD and SiGe:C HBT processes — with active interest in FinFET, GAAFET, GaAs pHEMT, GaN HEMT and InSb DHBT. The full flow is covered in-house: specification, design, verification, layout, packaging and characterization. Design capabilities: - Analog — comparators, level shifters, OpAmps, reference oscillators, CTAT/PTAT sensors, bandgap and beta-multiplier references, Ivanov regulators, offset and noise minimization. - Digital — Verilog/VHDL design and synthesis with Cadence Genus; FSM, decimation-filter, MIPI CSI / SPI and SRAM integration. - Electromagnetic — on-chip antennas and passives with 2.5D MoM solvers (Cadence EMX, Keysight Momentum, Sonnet). - High-voltage / power — high-dv/dt gate drivers for IGBT, SiC and GaN; voltage multiplier rectifiers; 3-phase inverters. - Mixed-signal — high-accuracy and high-speed ADCs (extended counting, SAR, CT/DT Σ/Δ, flash, folding, pipeline), DACs and integer-N / fractional-N MASH PLLs. - RF (< 6 GHz) — multi-band, multi-mode 2G/3G/4G/5G cellular transceivers and front-end modules with carrier aggregation and MIMO. - mmW (> 24 GHz) — FMCW and pulse-Doppler radar transceivers, VSAT receivers, phased arrays and T/R modules for 5G base stations. Verification and back-end: Cadence Spectre FX and Xcelium for mixed-signal verification; PVS/Pegasus or Siemens Calibre for DRC/LVS/PEX; Siemens Solido for PVT/MC yield optimization. Package and PCB signal integrity with Ansys Q3D, HFSS and CST. On-wafer characterization (S-parameter, NF, ACPR, IP3, P1dB) and FIB debugging, plus qualification and production-test support. PRODUCTS: ChipDesign B.V. is developing ICs for defense applications—specifically for guidance and ISR.