Senior Semiconductor packaging engineer @ (May 2026 - June 2026)
Semiconductor Packaging Engineer @ (January 2023 - May 2026)
Graduate Research Assistant @ (January 2021 - December 2022)
Research Intern @ (January 2019 - June 2019)
Research Intern @ (May 2018 - July 2018)
Chintan Patel Education
Nirma University
Bachelor's degree (Mechanical Engineering)
University of Maryland
Master's degree (Mechanical Engineering)
Chintan Patel Skills
8D Problem Solving
ANSYS
ANSYS (LS DYNA, Icepak, Sherlock, Fluent, Additive Suite & Structural)
Accelerated Life Testing
Arduino
COMSOL
Chip package interaction
Continuous Improvement
Design for Six Sigma (DFSS)
Design for reliability
Design of Experiments (DOE)
Electronics Packaging
Event tree method
Failure Analysis
Failure Mode and Effects Analysis (FMEA)
Finite Element Analysis
Gear Manufacturing
HVAC
Heterogeneous integration (HI)
IC packaging
Jira
KiCAD
LabVIEW
LangChain
Laser assisted bonding
Lean Manufacturing
MATLAB
New Product Introduction
OSAT Management
Package Module Design
Pricing Strategy
Probabilistic Physics of Failure Models
Product Reliability
Python
Reliability Centered Maintenance
SAP ERP
SCADA
SI/PI analysis
Shell & Tube Heat Exchangers
Siemens NX
Simulink
SolidWorks
Spectroscopy
Statistical Process Control (SPC)
Substrate design
Tableau
Thermal Management
Thermal simulation
Chintan Patel Summary
Chintan Patel, based in San Jose, CA, US, is currently a Staff Photonics Packaging Engineer at Aeva. Chintan Patel brings experience from previous roles at Analog Devices, Center for Advanced Life Cycle Engineering (CALCE) and Amul (GCMMF). Chintan Patel holds a Bachelor's degree in Mechanical Engineering @ Nirma University. With a robust skill set that includes 8D Problem Solving, ANSYS, ANSYS (LS DYNA, Icepak, Sherlock, Fluent, Additive Suite & Structural), Accelerated Life Testing, Arduino and more. Chintan Patel has 2 emails on RocketReach.
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