Senior Verification IP Engineer @ (August 2021 - July 2023)
Senior Verification IP Engineer @ (January 2020 - July 2023)
Senior Verification IP Engineer (PHY Project Lead) @ (July 2017 - July 2023)
Verification IP Engineer @ (December 2015 - July 2017)
Chih Cheng Education
國立清華大學
碩士 (電機工程學系)
2013-2015
Chih Cheng Skills
CXL
AMBA
Functional Verification
PCIe Specification
SystemVerilog
Shell Scripting
Perl
Verilog
Universal Verification Methodology (UVM)
Debugging
Chih Cheng Summary
Chih Cheng, based in San Jose, CA, US, is currently a Software Engineer (Verification IP) at Siemens EDA (Siemens Digital Industries Software). Chih Cheng brings experience from previous roles at Avery Design Systems. Chih Cheng holds a 2013 - 2015 碩士 in 電機工程學系 @ 國立清華大學. With a robust skill set that includes CXL, AMBA, Functional Verification, PCIe Specification, SystemVerilog and more. Chih Cheng has 2 emails and 1 mobile phone numbers on RocketReach.
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