Chen Cui Location
- Santa Clara, CA, US
Chen Cui Work
- 2019 - now ASIC Design Eng 4 @
- 2017 - 2019 SEG integration @
- 2013 - 2017 ASIC Design Engineer @
- 2012 - 2012 Grader of EE577a @
- 2011 - 2012 MS student major in EE @
Chen Cui Education
- University of Electronic Science and Technology
Bachelor's degree (Micro-electronics)
2007 - 2011 - University of Southern California
Chen Cui Skills
- C/C++
- Cache Coherence
- Linux/Unix Environment
- Cadence Virtuoso
- Computer Architecture
- LTSpice
- System Verilog
- Cacti
- ASIC
- Tomasulo
- Ncverilog
- Simplescalar
- ModelSim
- Synopsys tools
- Cadence Spectre
- Design
- Vlsi Design
- Analysis
- Sram And Dram
- Asic Design
- Verilog/Vhdl
Chen Cui Summary
- Chen Cui, based in Santa Clara, CA, US, is currently a ASIC Design Eng 4 at Apple. Chen Cui brings experience from previous roles at Apple, Marvell Semiconductor and University of Southern California. Chen Cui holds a 2007 - 2011 Bachelor's degree in Micro-electronics @ University of Electronic Science and Technology. With a robust skill set that includes C/C++, Cache Coherence, Linux/Unix Environment, Cadence Virtuoso, Computer Architecture and more. Chen Cui has 2 emails and 3 mobile phone numbers on RocketReach.
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