Chen-Chi Lo Email
ASIC performance architect @ Google
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Chen-Chi Lo Location
- Taipei, Taiwan
Chen-Chi Lo Work
- 2020 -now ASIC performance architect @
- 2019 -2020 Senior Staff Engineer @
- 2018 -2019 Senior Manager @
- 2017 -2018 Senior ASIC manager and Project Leader @
- 2016 -2017 SoC Architect and Project Leader @
- 2012 -2016 Performance Architect @
- 2007 -2012 Senior Engineer @
Chen-Chi Lo Education
- 國立臺灣大學
M.S. with Distinction, DSP and Communications (Electrical Engineering)
2005-2007 - 國立交通大學
B.S., Communications Engineering (Electrical Engineering)
2001-2005
Chen-Chi Lo Skills
- Semiconductors
- Embedded Systems
- IC
- ASIC
- SoC
- Debugging
- C
- C++
- Verilog
- Embedded Software
- 现场可编程逻辑门阵列
- FPGA
- EDA
- Programming
- VLSI
- ARM
- Digital Signal Processors
- Device Drivers
- Firmware
- Analog
- CMOS
- Simulations
- Electronics
- RTL Design
- Perl
- Mixed Signal
- Leadership
- Sales
- Microsoft Office
- Training
- Change Management
- Project Planning
- Software Development
- Cross Functional Team Building
- Cross Functional Team Leadership
Chen-Chi Lo Summary
- Chen-Chi Lo, based in Taipei, Taiwan, is currently a ASIC performance architect at 谷歌. Chen-Chi Lo brings experience from previous roles at SiFive, Bitmain and Montage Technology, Inc. Chen-Chi Lo holds a 2005 - 2007 M.S. with Distinction, DSP and Communications in Electrical Engineering @ 國立臺灣大學. With a robust skill set that includes Semiconductors, Embedded Systems, IC, ASIC, SoC and more. Chen-Chi Lo has 3 emails on RocketReach.
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Chen-Chi Lo
ASIC performance architect
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