Chee Ooi Email
SMTS Silicon Design Engineer @ AMD
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Chee Ooi Location
- Penang, Malaysia
Chee Ooi Work
- SMTS Silicon Design Engineer @ (June 2024 - Present)
- Design Engineer @ (March 2018 - June 2024)
- Expert R and D FPGA Engineer @ (December 2014 - February 2018)
- Sr Design Engineer @ Altera (September 2008 - October 2013)
Chee Ooi Education
- Universiti Tun Hussein Onn Malaysia
Electrical Electronic (Computer Engineering)
2000-2005
Chee Ooi Skills
- RTL qualification
- FPGA prototyping
- FPGA emulation
- FPGA Application Design
- Fusion Compiler
- PCIe IP
- Soc Design
- Lint CDC RDC
- RTL Front End Design
- TFM
- C++ Language
- Verilog
- SystemVerilog
- FPGA
- ModelSim
- Functional Verification
- DDR3
- Nios II
- Ethernet Mac (Triple Speed Ethernet)
Chee Ooi Summary
- Chee Ooi, based in Penang, Malaysia, is currently a SMTS Silicon Design Engineer at AMD. Chee Ooi brings experience from previous roles at Intel Corporation, Keysight Technologies and Altera. Chee Ooi holds a 2000 - 2005 Electrical Electronic in Computer Engineering @ Universiti Tun Hussein Onn Malaysia. With a robust skill set that includes RTL qualification, FPGA prototyping, FPGA emulation, FPGA Application Design, Fusion Compiler and more. Chee Ooi has 2 emails on RocketReach.
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