Charapov Alexandre's Location
Beverly Hills, CA, US
Charapov Alexandre's Work
- Staff Engineer @ Qualcomm
- ASIC Design Engineer - contractor @ TexasInstruments
- Principal ASIC Design Engineer @ Jaalaa Inc.
- Senior ASIC Design Engineer @ Microtune
- FPGA Design Engineer @ Redline Communications (now Aviat Networks)
- ASIC Design Engineer @ Nortel Networks
- FPGA Design Engineer @ Spacebridge Networks, Newbridge affiliated company
- FPGA Design Engineer @ Rockwell Semiconductor Systems Division
- Microelectronic Circuit Design Engineer @ Gambit Co., (forerunner of present Rockwell Semiconductor Systems),
- ASIC Design Engineer and Software Design Engineer @ Scientific Research Center (Former USSR Scientific Center)
Charapov Alexandre's Education
- San Diego State University-California State University
Master of Engineering - MEng (Electrical and Electronics Engineering)
2012 - 2017 - Institute for Information Transmission Problems
Ph. D. candidate
1989 - 1991 - Moscow Institute of Physics and Technology
Master of Science (MS) (Automated Control Systems)
1983 - 1989
- Moscow Institute of Physics and Technology (State University) (MIPT)
Master's Degree (Electrical and Electronics Engineering)
1983 - 1989 - San Diego State University-California State University
Charapov Alexandre's Skills
- Verilog
- ASIC
- Embedded Systems
- Debugging
- FPGA
- Sta
- Matlab
- VHDL
- TCL
- Perl
Charapov Alexandre's Summary
Charapov Alexandre, based in Beverly Hills, CA, US, is currently a Staff Engineer at Qualcomm, bringing experience from previous roles at TexasInstruments, Jaalaa Inc., Microtune and RedLine Communication. Charapov Alexandre holds a 2012 - 2017 Master of Engineering - MEng in Electrical and Electronics Engineering @ San Diego State University-California State University. With a robust skill set that includes Verilog, ASIC, Embedded Systems, Debugging, FPGA and more, Charapov Alexandre contributes valuable insights to the industry. Charapov Alexandre has 1 email on RocketReach.
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