Chaoyu Yen Email & Phone Number
FPGA Silicon Design Engineer @ Intel Federal LLC
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Chaoyu Yen Location
- San Ramon, CA, US
Chaoyu Yen Work
- FPGA Silicon Design Engineer @ (April 2022 - Present)
- SoC Design Engineer @ (November 2015 - April 2022)
- Senior Member of Technical Staff @ Altera (April 2013 - November 2015)
- Member of Technical Staff @ Altera (March 2011 - March 2013)
- Design Verification Engineer @ Netlist, Inc. (September 2010 - March 2011)
- Sr. Arch. Modeling Engineer @ (November 2005 - September 2010)
- Architecture Validation Engineer @ (October 2001 - November 2005)
- Software Engineer @ Tesaria Inc. (Symmetry Communications Systems) (January 2001 - January 2001)
Chaoyu Yen Education
- Syracuse University
MS (Computer Engineering)
1999-2000
Chaoyu Yen Skills
- ASIC
- Debugging
- Verilog
- Semiconductors
- ARM
- Architectures
- C++
- FPGA
- SoC
- Embedded Systems
- Design
- Design Engineering
Chaoyu Yen Summary
- Chaoyu Yen, based in San Ramon, CA, US, is currently a FPGA Silicon Design Engineer at Intel Federal LLC. Chaoyu Yen brings experience from previous roles at Intel Corporation, Altera and Netlist, Inc.. Chaoyu Yen holds a 1999 - 2000 MS in Computer Engineering @ Syracuse University. With a robust skill set that includes ASIC, Debugging, Verilog, Semiconductors, ARM and more. Chaoyu Yen has 1 emails and 1 mobile phone numbers on RocketReach.
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