Cecilia Li's Location
Toronto, ON, CA
Cecilia Li's Work
- SOC Design Engineering Manager @ Intel Corporation
- Technical Lead @ Intel Corporation
- SOC Design Engineer @ Intel Corporation
- Staff ASIC Physical Design Engineer @ ViXS Systems Inc.
- Sr. ASIC Physical Design Engineer @ ViXS Systems Inc.
- ASIC Physical Design Engineer @ ViXS Systems Inc.
- ASIC and CAD Methodology Engineer @ AMD
Cecilia Li's Education
- University of Toronto
BASC (Electrical Engineering)
2000 - 2005
Cecilia Li's Skills
- Timing Closure
- Static Timing Analysis
- ASIC
- Physical Design
- SoC
- Physical Verification
- FPGA
- Floorplanning
- RTL design
- VLSI
Cecilia Li's Summary
Cecilia Li, based in Toronto, ON, CA, is currently a SOC Design Engineering Manager at Intel Corporation, bringing experience from previous roles at Intel Corporation and ViXS Systems Inc.. Cecilia Li holds a 2000 - 2005 BASC in Electrical Engineering @ University of Toronto. With a robust skill set that includes Timing Closure, Static Timing Analysis, ASIC, Physical Design, SoC and more, Cecilia Li contributes valuable insights to the industry. Cecilia Li has 3 emails on RocketReach.
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