CadEnhance Information

CadEnhance provides low cost productivity tools for all sizes of Hardware Design and Development Organizations. The tools have been developed over time to enhance the capability and maximize the efficiency of the customer's existing EDA tools. We bring Automation to Electronic Design. PartBuilder automates schematic Symbol Generation for high Pin count electronic devices. It turns a typically repetitive interactive chore into a streamlined intuitive design process. Build symbols for any FPGA from 100-4000+ pins in less than an hour. Large ASICS take ~1 hour/1000 Pins, Large connectors take minutes. Supports AllegroHDL, Orcad, DxDesigner and PADS professional, Altium, Eagle and Zuken design Tools CE-HDL automates connection and symbol placement in Allegro HDL schematics. Accurately connect FPGAS and large ASICS, saving HW Designers hundreds of hours in a large design. SchChk for Allegro-HDL finds errors early in the schematic design process and provides streamlined symbol generation for Hierarchical blocks to eliminate one of the bigger manual interactive processes facing designers today. NetBom tool can be used to compare Netlists and BOMs from 2 different revisions of a board design and summarize the differences in a concise easy to understand format that is invaluable in design reviews.